ADF4116BRUZ View Datasheet(PDF) - Analog Devices
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ADF4116BRUZ Datasheet PDF : 20 Pages
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ADF4116/ADF4117/ADF4118
Table VII. Initialization Latch Map
RESERVED
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
X PD2
X
X
X
TC4 TC3 TC2 TC1
F6
X
DB9
F4
DB8
F3
DB7
F2
DB6
M3
DB5
M2
DB4
M1
DB3
PD1
DB2 DB1 DB0
F1 C2 (1) C1 (1)
CE PIN PD2 PD1
MODE
0
X X ASYNCHRONOUS POWER-DOWN
1
X 0 NORMAL OPERATION
1
0 1 ASYNCHRONOUS POWER-DOWN
1
1 1 SYNCHRONOUS POWER-DOWN
TC4
TC3
TC2
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
F1
COUNTER
OPERATION
0 NORMAL
1
R, A, B COUNTERS
HELD IN RESET
M3
M2
M1
OUTPUT
0
0
0
THREE-STATE OUTPUT
0
0
0
1
0
1
1
0
DIGITAL LOCK DETECT
1
(ACTIVE HIGH)
0
N DIVIDER OUTPUT
1
AVDD
0
R DIVIDER OUTPUT
ANALOG LOCK DETECT
1
0
1
(N CHANNEL OPEN DRAIN)
SERIAL DATA OUTPUT
1
1
0
(INVERSE POLARITY OF
SERIAL DATA INPUT)
1
1
1
DGND
F2 PD POLARITY
0
NEGATIVE
1
POSITIVE
F3
CHARGE PUMP
OUTPUT
0 NORMAL
1 THREE-STATE
F4
F6
FASTLOCK MODE
0
X FASTLOCK DISABLED
1
0 FASTLOCK MODE 1
1
1 FASTLOCK MODE 2
TIMEOUT
TC1
(PFD CYCLES)
0
3
1
7
0
11
1
15
0
19
1
23
0
27
1
31
0
35
1
39
0
43
1
47
0
51
1
55
0
59
1
63
REV. 0
–15–
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