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LC74201JE View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
View to exact match
LC74201JE
SANYO
SANYO -> Panasonic SANYO
LC74201JE Datasheet PDF : 21 Pages
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LC74201JE
Clock Pins
Pin No.
18
Symbol
FSCO
I/O
Logic
Function
Out
Positive
Subcarrier clock output (frequency = 1/4 pixel clock frequency). Tristate output using DVDD2 (5-V) power
supply.
19
PCKO
Out Positive Pixel clock output (NTSC-4fsc, PAL-4fsc, or 13.5 MHz). Tristate output using DVDD1 (4-V) power supply.
55
XPALIN
In
56
XPALOUT Out
568
XNTIN
In
59
XNTOUT
Out
Crystal oscillator connections for PAL-4fsc oscillation circuit (4fsc = 17.734475 MHz)
Crystal oscillator connections for NTSC-4fsc oscillation circuit (4fsc = 14.31818 MHz)
61
CLKSEL
In
Positive
Clock selection control input. High: 54.0-MHz clock input from pin 62 (CLKIN); Low: clock from internal
VCO oscillator.
62
CLKIN
In
Positive 54.0-MHz clock input (with built-in bias). When not used, connect to DVDD1 or DVSS1.
63
VCOR
Adjustment resistor connection for VCO oscillator circuit.
66
PLLFIL
PLL filter connection
68
CDCK
In
Positive CD-DSP clock input (16.9344, 2.8224, or 2.1168 MHz)
Microcontroller Interface
Pin No.
38
41
Symbol
RESET
IRQ
I/O
Logic
Function
In Negative System reset input (Hysteresis input; built-in pull-up resistor).
Out Negative Interrupt request signal output (N-channel open-drain output).
43
AS/DS (CE)
In
Positive
Parallel interface: Address/data select input (Low = address).
Serial interface: Serial transfer enable signal input (High = enabled).
44
STB (CL)
In
Positive
Parallel interface: Strobe signal input for address input and data I/O.
Serial interface: Serial transfer clock signal input.
45
AD0 (DO)
I/O
Positive
Parallel interface: Address/data I/O port P0 (LSB).
Serial interface: ZPSerial data output (LSB-first input).
46
AD1 (DI)
I/O
Positive
Parallel interface: Address/data I/O port P1.
Serial interface: Serial data input (LSB-first output).
47
AD2
I/O Positive
Parallel interface: Address/data I/O ports.
48
AD3
I/O Positive The interface mode is determined at the release of the system reset.
The mode is determined by setting the three bits of AD3, AD4, and AD5.
49
AD4
I/O Positive
• Serial interface: AD5:AD4:AD3 = 1:*:* (* = Don’t care)
50
AD5
I/O Positive • Parallel interface: AD5:AD4:AD3 = 0:1:0 or 0:1:1 or 0:0:0
51
AD6
I/O Positive AD7: Parallel interface address/data I/O port P7 (MSB).
52
AD7 (MBS) I/O Positive
Note: AD0 to AD7 use N-channel open-drain outputs.
No. 5761-4/21
 

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