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TDA10085HT View Datasheet(PDF) - Philips Electronics

Part Name
Description
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TDA10085HT
Philips
Philips Electronics Philips
TDA10085HT Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Philips Semiconductors
Single chip DVB-S/DSS channel receiver
10 APPLICATION INFORMATION
Product specification
TDA10085HT
handbook, full pagewidth
from
LNB
MIXER
×
LO
PLL
90° PHASE
SHIFT
×
MIXER
VAGC XIN
30
1
VIN1
15
XOUT
2
51-54 8
59-62
DO[7-0]
VREFP
14
50
TDA10085HT
VREFN 13
49
OCLK
DEN
48
GND
VIN2
47
12
28
29
32 33
SDA-0 SCL-0 SDA SCL
UNCOR
PSYNC
MGU428
The TDA10085 can receive a 4 MHz clock signal delivered by the PLL synthesizer, or can generate the sampling clock from a crystal connected
between XIN and XOUT.
Bypass capacitors (0.1 µF) should be placed close to ADC voltage references VREFP and VREFN.
Fig.3 Front-end receiver schematic.
handbook, full pagewidth
LNB SUPPLY
GENERATION
VAGC CTRL1
22K
30
21
63
VIN1
LNB
channel I
TUNER
channel Q
15
VIN2
12
TDA10085
51-54 MPEG2
59-62
8
transport
stream
DO[7-0]
28
29
32 33
SDA-0 SCL-0 SDA SCL
MGU429
2001 Aug 31
Fig.4 Typical use of CTRL1 and 22K outputs.
11
 

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