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ML2036IS View Datasheet(PDF) - Micro Linear Corporation

Part NameDescriptionManufacturer
ML2036IS Serial Input Programmable Sine Wave Generator with Digital Gain Control Micro-Linear
Micro Linear Corporation Micro-Linear
ML2036IS Datasheet PDF : 12 Pages
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The ML2035 is composed of a programmable frequency
generator, a sine wave generator, a crystal oscillator, and a
serial digital interface. The ML2036 frequency and sine
wave generator functional block diagram is shown in
Figure 4.
The programmable frequency generator produces a digital
output whose frequency is determined by a 16-bit digital
The frequency generator is composed of a phase
accumulator which is clocked at fCLK IN/4. The value
stored in the data latch is added to the phase accumulator
every 4 cycles of CLK IN. The frequency of the analog
output is equal to the rate at which the accumulator
overflows and is given by the equation:
0 5 fOUT
D15 D0 DEC
The frequency resolution and the minimum frequency are
the same and is given by the following equation:
When fCLK IN = 12.352MHz, DfMIN = 1.5Hz (±0.75Hz).
Lower frequencies are obtained by using a lower input
clock frequency.
Due to the phase quantization nature of the frequency
generator, spurious tones can be present in the output
range of –55dB relative to fundamental. The energy from
these tones is included in the signal to noise + distortion
specification. The frequency of these tones can be very
close to the fundamental. Therefore, it is not practical to
filter them out.
The sine wave generator is composed of a sine look-up
table, a DAC, and an output smoothing filter. The sine
look-up table is addressed by the phase accumulator. The
DAC is driven by the output of the look-up table and
generates a staircase representation of a sine wave.
The output filter smoothes the analog output by removing
the high frequency sampling components. The resultant
voltage on VOUT is a sinusoid with the second and third
harmonic distortion components at least 45dB below the
The ML2036 has a VREF input that can be tied to VCC or
generated from an external voltage. With the GAIN input
equal to a logic "1", the sine wave peak-to-peak voltage is
equal to ±VREF; with the GAIN equal to a logic "0", the
peak voltage is ±VREF/2. However, the overall output
voltage swing is limited to no closer than 1.5V to either
rail. This means that to avoid clipping, VREF can only be
tied to VCC when GAIN is a logic "0". The sinewave output
is referenced to AGND.
The analog section is designed to operate over a range
from DC to 50kHz. Due to slew rate limitations, the peak-
to-peak output voltage must be limited to VOUT(P-P) £
(125kV x Hz)/fOUT. For example, an output at 50kHz must
be limited to 2.5VP-P. VOUT can drive a 1kW, 100pF load
and swing to within 1.5V of VCC and VSS, provided the
slew rate limitations mentioned above are not exceeded.
The output offset voltage, VOS, is a function of the peak-to-
peak output voltage and is specified as:
  0 5 VOS MAX = ±
0 5 2.5 + VOUT PP
For example, if VOUT(P-P) = 2.5V:
  0 5 VOS MAX = ±
2.5 + 2.5
= ±50mV
The crystal oscillator generates an accurate reference
clock for the programmable frequency generator. The
internal clock can be generated with a crystal or external
If a crystal is used, it must be placed between CLK IN and
DGND of the ML2036. An on-chip crystal oscillator will
then generate the internal clock. No other external
capacitors or components are required. The crystal should
be a parallel-resonant type with a frequency between
3MHz to 12.4MHz. It should be placed physically as close
as possible to the CLK IN and DGND.
An external clock can drive CLK IN directly if desired. The
frequency of this clock can be anywhere between 0 and
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 5. Serial Interface Timing.
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