CAT25C128K-1.8TE13 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi
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CAT25C128K-1.8TE13 Datasheet PDF : 11 Pages
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CAT25C128/256
WRITE Sequence
The CAT25C128/256 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruc-
tion must be sent to CAT25C128/256. The device goes
into Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C128/256.
The CS must be brought high after the WREN instruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Figure 4. Read Instruction Timing
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address (the most significant bit is don't care for
25C256 and the two most significant bits are don't care
for the 25C128), and then the data to be written. Pro-
gramming will start after the CS is brought high. The low
to high transition of the CS pin must occur during the
SCK low time, immediately after clocking the least
significant bit of the data. Figure 6 illustrates byte write
sequence.
CS
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
SI
0000001 1
BYTE ADDRESS*
SO
HIGH IMPEDANCE
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
DATA OUT
7 6 5 432 1 0
MSB
Figure 5. RDSR Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
1
0
1
DATA OUT
7
6
5
4
32
10
MSB
Doc. No. 25088-00 1/01
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