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ADM1022(2003) View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADM1022 Datasheet PDF : 21 Pages
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ADM1022
Parameter
Min Typ Max Unit
Test Conditions
DIGITAL INPUT LOGIC LEVELS
(FAN_SPD/NTEST_IN,
ADD/NTEST_OUT, MR, GPI)
Input High Voltage, VIH
Input Low Voltage, VIL
2.2
V
0.8
V
DIGITAL INPUT LEAKAGE CURRENT
(ALL DIGITAL INPUTS)
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING3
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU:STA
Start Hold Time, tHD:STA
Stop Condition Setup Time, tSU:STO
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU:DAT
Data Hold Time, tHD:DAT
–1
–0.005
mA
+0.005 +1
mA
5
pF
400
kHz
50
ns
1.3
ms
600
ns
600
ns
600
ns
1.3
ms
0.6
ms
300
ns
300
ns
100
ns
300
ns
VIN = VCC
VIN = 0
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
NOTES
1Typicals are at TA = 25C and represent most likely parametric norm. Standby current typ is measured with V CC = 3.3 V.
2ADD is a three-state input that may be pulled high, low or left open-circuit.
3Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Specifications subject to change without notice.
SCLK
tLOW tR
tF
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tHD;STA
tSU;STA
SDATA
tBUF
P
S
S
Figure 1. Diagram for Serial Bus Timing
tSU;STO
P
REV. B
–3–
 

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