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ADM1024ARU-REEL View Datasheet(PDF) - Analog Devices

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ADM1024ARU-REEL Datasheet PDF : 32 Pages
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ADM1024
Table XII. Register 43h, INT Interrupt Mask Register 1 (Power-On Default = 00h)
Bit Name
0 2.5 V/Ext. Temp2
1
VCCP1
2 VCC
3 5V
4 Int. Temp
5 Ext. Temp1
6 FAN1/AIN1
7 FAN2/AIN2
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
Bit Name
0 12 V
1
VCCP2
2 Reserved
3 Reserved
4 CI
5 THERM (Input)
6 D1 Fault
7 D2 Fault
Table XIII. Register 44h, INT Mask Register 2 (Power-On Default = 00h)
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
Power-Up Default Set to Low
Power-Up Default Set to Low
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
A 1 disables the corresponding interrupt status bit for INT interrupt.
Bit Name
0–6 Reserved
7 Chassis Int. Clear
Table XIV. Register 46h, Chassis Intrusion Clear (Power-On Default = 00h)
R/W
Description
Read Only
Read/Write
Undefined, always reads as 00h
A 1 outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The regis-
ter bit clears itself after the pulse has been output.
Table XV. Register 47h, VID0–3/FAN Divisor Register (Power-On Default = 0101(VID3–0))
Bit Name
R/W
Description
0–3 VID
4–5 FAN1 Divisor
6–7 FAN2 Divisor
Read
Read/Write
Read/Write
The VID<3:0> inputs from processor core power supplies to indicate the operating
voltage (e.g., 1.3 V to 3.5 V).
Sets counter prescaler for FAN1 speed measurement.
<5:4> = 00 – divide by 1.
<5:4> = 01 – divide by 2.
<5:4> = 10 – divide by 4.
<5:4> = 11 – divide by 8.
Sets counter prescaler for FAN2 speed measurement.
<7:6> = 00 – divide by 1.
<7:6> = 01 – divide by 2.
<7:6> = 10 – divide by 4.
<7:6> = 11 – divide by 8.
Bit Name
0 VID4
1–7 Reserved
Table XVI. Register 49h, VID4/Device ID Register (Power-On Default = 1000000(VID4))
R/W
Description
Read Only
Read Only
VID4 Input from Pentium
Undefined, always reads as 1000 000(VID4)
REV. B
–27–
 

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