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LC72723M View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
View to exact match
LC72723M
SANYO
SANYO -> Panasonic SANYO
LC72723M Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
LC72723, LC72723M
5. When switching channels, it is desirable to immediately reset memory and the READY pin with an RST input. If this is not done, data received on the
previous channel may remain in memory. When the IC is reset, data is not written until the RDS-ID is detected, and therefore, the READY signal will go
low after the RDS-ID is detected. (Although the RDS-ID is not output in slave mode, it is detected internally in the IC.) After an RST input, once an RDS-
ID has been detected, all received data will be written to memory regardless of the RDS-ID detection state.
6. The readout mode may be switched between master and slave modes during readout. Applications must observe the following points to assure data
continuity during this operation.
• Data acquisition timing in master mode
Data must be read on the falling edge of RDCL.
• Timing of the switch from master mode to slave mode
After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE high immediately. Then, the microcontroller
starts output by setting the RDCL signal low. The microcontroller RDCL output must start within 840 µs (tms) after RDCL went low. In this case, if the
last data read in master mode was data item n, then data starting with item n+1 will be written to memory.
• Timing of the switch from slave mode to master mode
After all data has been read from memory and READY has gone high, the application must then wait until READY goes low once again the next time
(timing A in the figure), immediately read out one bit of data and input the RDCL clock. Then, at the point READY goes high, the microcontroller must
terminate RDCL output and then set MODE low. The application must switch MODE to low within 840 µs (tms) after READY goes low (timing A in the
figure).
RDCL (microcontroller status)
RDCL (IC status)
No. 6037-7/8
 

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