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M38861F5A-XXXGP View Datasheet(PDF) -

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M38861F5A-XXXGP
 
M38861F5A-XXXGP Datasheet PDF : 0 Pages
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3886 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the
processor mode bits specifying the chip operation mode, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode (Note)
1 0 : Microprocessor mode (Note)
1 1 : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Reserved
(Do not write “0” to this bit when using
XCIN–XCOUT oscillation function.)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Note: This mode is not available for M38869M8A/MCA/MFA and the flash memory version.
Fig. 7 Structure of CPU mode register
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
9
 

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