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M38860E2A-XXXFS View Datasheet(PDF) -

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M38860E2A-XXXFS
 
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
STSP
SEL
SIS
SIP SSC4 SSC3 SSC2 SSC1 SSC0
I2C START/STOP condition
control register
(S2D : address 001716)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
START/STOP condition generating
selection bit
0 : Setup/Hold time short mode
1 : Setup/Hold time long mode
Fig. 45 Structure of I2C START/STOP condition control register
Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
10
Main clock
divide ratio
2
System
clock φ
(MHz)
5
8
2
4
8
8
1
4
2
2
2
2
1
START/STOP
condition
control register
XXX11110
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
SCL release time
(µs)
6.2 µs (31 cycles)
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
Setup time
(µs)
3.2 µs (16 cycles)
3.5 µs (14 cycles)
3.25 µs (13 cycles)
3.0 µs (3 cycles)
3.5 µs (7 cycles)
3.0 µs (6 cycles)
3.0 µs (3 cycles)
Hold time
(µs)
3.0 µs (15 cycles)
3.25 µs (13 cycles)
3.0 µs (12 cycles)
2.0 µs (2 cycles)
3.0 µs (6 cycles)
2.5 µs (5 cycles)
2.0 µs (2 cycles)
Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
S Slave address R/W A Data A Data A/A P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S Slave address R/W A Data A Data A P
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd bytes
A
Data
A
Data A/A P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd bytes
A
Sr
Slave address
1st 7 bits
R/W
A
Data
A
Data
A
P
7 bits
“0”
8 bits
7 bits
“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
1 to 8 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
Fig. 46 Address data communication format
48
 

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