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M38860E3A-XXXGP
 
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I2C status
register (address 001416) at the same time after writing the slave
address to the I2C data shift register (address 001216) with the
condition in which the ES0 bit of the I2C control register (address
001516) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “0002” and an SCL for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 41, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
I2C status register
write signal
SC L
SD A
Setup
time
Hold time
Fig. 41 START condition generating timing diagram
Table 11 START condition generating timing table
Item
Setup
time
Hold
time
START/STOP condition Standard
generating selection bit clock mode
High-speed
clock mode
“0”
5.0 µs (20 cycles) 2.5 µs (10 cycles)
“1”
13.0 µs (52 cycles) 6.5 µs (26 cycles)
“0”
5.0 µs (20 cycles) 2.5 µs (10 cycles)
“1”
13.0 µs (52 cycles) 6.5 µs (26 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
STOP Condition Generating Method
When the ES0 bit of the I2C control register (address 001516) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I2C status register (address 001416) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 42, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
I2C status register
write signal
SC L
SD A
Setup
time
Hold time
Fig. 42 STOP condition generating timing diagram
Table 12 STOP condition generating timing table
Item
Setup
time
Hold
time
START/STOP condition Standard
generating selection bit clock mode
High-speed
clock mode
“0”
5.5 µs (22 cycles) 3.0 µs (12 cycles)
“1”
13.5 µs (54 cycles) 7.0 µs (28 cycles)
“0”
5.5 µs (22 cycles) 3.0 µs (12 cycles)
“1”
13.5 µs (54 cycles) 7.0 µs (28 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 43, 44, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I2CIRQ” occurs to the CPU.
SC L
SD A
BB flag
SCL release time
Setup
time
Hold time
BB flag
reset
time
Fig. 43 START condition detecting timing diagram
SC L
SD A
BB flag
SCL release time
Setup
time
Hold time
BB flag
reset
time
Fig. 44 STOP condition detecting timing diagram
Table 13 START condition/STOP condition detecting conditions
Standard clock mode
High-speed clock mode
SCL release time SSC value + 1 cycle (6.25 µs) 4 cycles (1.0 µs)
Setup time
SSC value
2
+ 1 cycle < 4.0 µs (3.25 µs)
2 cycles (1.0 µs)
Hold time
SSC value
2
cycle < 4.0 µs (3.0 µs)
2 cycles (0.5 µs)
BB flag set/
reset time
SSC
value
2
–1
+
2
cycles
(3.375
µs)
3.5 cycles (0.875 µs)
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
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