M38860E2A-XXXFS View Datasheet(PDF) -

MITSUBISHI MICROCOMPUTERS

3886 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

•Bit 6: Communication mode specification bit (transfer direc-

tion specification bit: TRX)

This bit decides a direction of transfer for data communication.

When this bit is “0,” the reception mode is selected and the data of

a transmitting device is received. When the bit is “1,” the transmis-

sion mode is selected and address data and control data are

output onto the SDA in synchronization with the clock generated on

the SCL.

This bit is set/reset by software and hardware. About set/reset by

hardware is described below. This bit is set to “1” by hardware

when all the following conditions are satisfied:

• When ALS is “0”

• In the slave reception mode or the slave transmission mode

• When the R/W bit reception is “1”

This bit is set to “0” in one of the following conditions:

• When arbitration lost is detected.

• When a STOP condition is detected.

• When writing “1” to this bit by software is invalid by the START

condition duplication preventing function (Note).

• With MST = “0” and when a START condition is detected.

• With MST = “0” and when ACK non-return is detected.

• At reset

•Bit 7: Communication mode specification bit (master/slave

specification bit: MST)

This bit is used for master/slave specification for data communica-

tion. When this bit is “0,” the slave is specified, so that a START

condition and a STOP condition generated by the master are re-

ceived, and data communication is performed in synchronization

with the clock generated by the master. When this bit is “1,” the

master is specified and a START condition and a STOP condition

are generated. Additionally, the clocks required for data communi-

cation are generated on the SCL.

This bit is set to “0” in one of the following conditions.

• Immediately after completion of 1-byte data transfer when arbi-

tration lost is detected

• When a STOP condition is detected.

• Writing “1” to this bit by software is invalid by the START condi-

tion duplication preventing function (Note).

• At reset

Note: START condition duplication preventing function

The MST, TRX, and BB bits is set to “1” at the same time after con-

firming that the BB flag is “0” in the procedure of a START condition

occurrence. However, when a START condition by another master

device occurs and the BB flag is set to “1” immediately after the con-

tents of the BB flag is confirmed, the START condition duplication

preventing function makes the writing to the MST and TRX bits in-

valid. The duplication preventing function becomes valid from the

rising of the BB flag to reception completion of slave address.

b7

b0

I2C status register

MST TRX BB PIN AL AAS AD0 LRB (S1 : address 001416)

Last receive bit (Note)

0 : Last bit = “0”

1 : Last bit = “1”

General call detecting flag

(Note)

0 : No general call detected

1 : General call detected

Slave address comparison flag

(Note)

0 : Address disagreement

1 : Address agreement

Arbitration lost detecting flag

(Note)

0 : Not detected

1 : Detected

I2C-BUS interface interrupt

request bit

0 : Interrupt request issued

1 : No interrupt request

issued

Bus busy flag

0 : Bus free

1 : Bus busy

Communication mode

specification bits

00 : Slave receive mode

01 : Slave transmit mode

10 : Master receive mode

11 : Master transmit mode

Note: These bit and flags can be read out but cannot

be written.

Write “0” to these bits at writing.

Fig. 39 Structure of I2C status register

SC L

PIN

I2CIRQ

Fig. 40 Interrupt request signal generating timing

45

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