M38860E2A-XXXFS View Datasheet(PDF) -

MITSUBISHI MICROCOMPUTERS

3886 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Data Setup (PWM0)

The PWM0 output pin also functions as port P30 or P56. The

PWM0 output pin is selected from either P30/PWM00 or

P56/PWM01 by bit 4 of the AD/DA control register (address

003416).

The PWM0 output becomes enabled state by setting bit 6 of the

port control register 1 (address 002E16). The high-order eight bits

of output data are set in the PWM0H register (address 003016)

and the low-order six bits are set in the PWM0L register (address

003116).

PWM1 is set as the same way.

PWM Operation

The 14-bit PWM data is divided into the low-order six bits and the

high-order eight bits in the PWM latch.

The high-order eight bits of data determine how long an “H”-level

signal is output during each sub-period. There are 64 sub-periods

in each period, and each sub-period is 256 ! τ (64 µs) long. The

signal is “H” for a length equal to N times τ, where τ is the mini-

Table 7 Relationship between low-order 6 bits of data and

period set by the ADD bit

Low-order 6 bits of data (PWML)

LSB

000000

000001

000010

000100

001000

010000

100000

Sub-periods tm Lengthened (m=0 to 63)

None

m=32

m=16, 48

m=8, 24, 40, 56

m=4, 12, 20, 28, 36, 44, 52, 60

m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62

m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63

mum resolution (250 ns).

“H” or “L” of the bit in the ADD part shown in Figure 30 is added to

this “H” duration by the contents of the low-order 6-bit data accord-

ing to the rule in Table 7.

That is, only in the sub-period tm shown by Table 7 in the PWM

cycle period T = 64t, its “H” duration is lengthened to the minimum

resolution τ added to the length of other periods.

For example, if the high-order eight bits of the 14-bit data are 0316

and the low-order six bits are 0516, the length of the “H”-level out-

put in sub-periods t8, t24, t32, t40, and t56 is 4 τ, and its length is 3

τ in all other sub-periods.

Time at the “H” level of each sub-period almost becomes equal,

because the time becomes length set in the high-order 8 bits or

becomes the value plus τ, and this sub-period t (= 64 µs, approxi-

mate 15.6 kHz) becomes cycle period approximately.

Transfer From Register to Latch

Data written to the PWML register is transferred to the PWM latch

at each PWM period (every 4096 µs), and data written to the

PWMH register is transferred to the PWM latch at each sub-period

(every 64 µs). The signal which is output to the PWM output pin is

corresponding to the contents of this latch. When the PWML regis-

ter is read, the latch contents are read. However, bit 7 of the

PWML register indicates whether the transfer to the PWM latch is

completed; the transfer is completed when bit 7 is “0” and it is not

done when bit 7 is “1.”

64 µs

m=0

64 µs

m=7

4096 µs

64 µs

m=8

64 µs

m=9

64 µs

m=63

15.75 µs

15.75 µs

15.75 µs

16.0 µs

Pulse width modulation register H :

00111111

Pulse width modulation register L :

000101

Sub-periods where “H” pulse width is 16.0 µs :

Sub-periods where “H” pulse width is 15.75 µs :

Fig. 30 PWM timing

15.75 µs

15.75 µs

m = 8, 24, 32, 40, 56

m = all other values

15.75 µs

33

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