M38860E3A-XXXGP View Datasheet(PDF) -
M38860E3A-XXXGP Datasheet PDF : 0 Pages
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Fig. 15 Interrupt control
Interrupt request
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
Not used (returns “0” when read)
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
Not used (returns “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0 Interrupt request register 1
b7
b0 Interrupt request register 2
(IREQ1 : address 003C16)
(IREQ2 : address 003D16)
INT0/input buffer full interrupt request
bit
INT1/output buffer empty interrupt
request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit/SCL, SDA interrupt
request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
CNTR0/SCL, SDA interrupt request bit
CNTR1/key-on wake-up interrupt
request bit
Serial I/O2/I2C interrupt request bit
INT2/I2C interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
AD converter/key-on wake-up interrupt
request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
b7
b0 Interrupt control register 2
(ICON2 : address 003F16)
INT0/input buffer full interrupt enable bit
INT1/output buffer empty interrupt
enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit/SCL, SDA interrupt
enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
CNTR0/SCL, SDA interrupt enable bit
CNTR1/key-on wake-up interrupt
enable bit
Serial I/O2/I2C interrupt enable bit
INT2/I2C interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
AD converter/key-on wake-up interrupt
enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers (1)
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