CD4011BMS View Datasheet(PDF) - Intersil
Part Name
Description
View to exact match
CD4011BMS Datasheet PDF : 9 Pages
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CD4011BMS, CD4012BMS, CD4023BMS
Schematic and Logic Diagrams
p
14 VDD
1*
n
(8, 6, 13)
p
2*
n
(9, 5, 12)
n
VDD
p
p
p
3 (10, 4, 11)
n
n
VSS
7 VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK
1(8, 6,13)
2(9, 5, 12)
1 OF 4 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
3
(10, 4, 11)
LOGIC DIAGRAM
CD4011BMS
3*(1, 11)
4*(2, 12)
5*(8, 13)
VDD 14
p
p
p
n
p
p
n
p
n
VDD
n
n
n
p
n 6(9, 10)
VSS 7
VSS
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK
3(1, 11)
1 OF 3 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
4(2, 12)
5(8, 13)
6
(9, 10)
LOGIC DIAGRAM
CD4023BMS
p
2*(12)
n
3*(11)
4*(10)
5*(9)
1 OF 2 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
14 VDD
p
n
p
n
p
n
n
n
n
2(12)
3(11)
p
4(10)
p
5(9)
p
1
(13)
LOGIC DIAGRAM
VDD
p
p
VSS
1
n (13)
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
n
NETWORK
7 VSS
CD4012BMS
7-59
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