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74ACQ374CW View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
74ACQ374CW Quiet Series™ Octal D-Type Flip-Flop with 3-STATE Outputs Fairchild
Fairchild Semiconductor Fairchild
74ACQ374CW Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
July 1989
Revised November 1999
74ACQ374 • 74ACTQ374
Quiet SeriesOctal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The ACQ/ACTQ374 is a high-speed, low-power octal D-
type flip-flop featuring separate D-type inputs for each flip-
flop and 3-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are common
to all flip-flops.
The ACQ/ACTQ374 utilizes FACT Quiet Seriestechnol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTOoutput control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Buffered positive edge-triggered clock
s 3-STATE outputs drive bus lines or buffer memory
address registers
s Outputs source/sink 24 mA
s Faster prop delays than the standard AC/ACT374
Ordering Code:
Order Number Package Number
Package Description
74ACQ374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ374QSC
MQA20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
74ACTQ374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
FACT, Quiet Series, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010238
www.fairchildsemi.com
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