SW06 View Datasheet(PDF) - Analog Devices

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SW06

Quad SPST JFET Analog Switch

Analog Devices 

SW06

Figure 1. Functional Applications of SW06

APPLICATIONS INFORMATION

The single analog switch product configures, by appropriate pin

connections, into four switch applications. As shown in Figure

1, the SW06 connects as a QUAD SPST, a DUAL SPDT, a

DUAL DPST, or a DPDT analog switch. This versatility in-

creases further when taking advantage of the disable input (DIS)

which turns all switches OFF when taken active low.

Ion-implantation of the JFET analog switch achieves low ON

resistance and tight channel-to-channel matching. Combining

the low ON resistance and low leakage currents results in a

worst case voltage error figure VERROR @ +125°C = ID(ON) ×

RSD(ON) = 100 nA × 100 Ω = 11 microvolts. This amount of er-

ror is negligible considering dissimilar-metal thermally-induced

offsets will be in the 5 to 15 microvolt range.

LOGIC INPUTS

The logic inputs (INX) and disable input (DIS) are referenced

to a TTL logic threshold value of two forward diode drops (1.4 V

at +25°C) above the GND terminal. These inputs use PNP

transistors which draw maximum current at a logic “0” level and

drops to a leakage current of a reverse biased diode as the logic

input voltage raises above 1.4 volts. Any logic input voltage

greater than 2.0 volts becomes logic “1,” less than 0.8 volts be-

comes logic “0” resulting in full TTL noise immunity not avail-

able from similar CMOS input analog switches. The PNP

transistor inputs require such low input current that the SW06

approaches fan-ins of CMOS input devices. These bipolar logic

inputs exceed any CMOS input circuit in resistance to static

voltage and radiation susceptibility. No damage will occur to the

SW06 if logic high voltages are present when the SW06 power

supplies are OFF. When the V+ and V– supplies are OFF, the

logic inputs present a reverse bias diode loading to active logic

inputs. Input logic thresholds are independent of V+ and V–

supplies making single V+ supply operation possible by simply

connecting GND and V– together to the logic ground supply.

ANALOG VOLTAGE AND CURRENT

ANALOG VOLTAGE

These switches have constant ON resistance for analog voltages

from the negative power supply (V–) to within 4 volts of the

positive power supply. This characteristic shown in the plots re-

sults in good total harmonic distortion, especially when com-

pared to CMOS analog switches that have a 20 to 30 percent

variation in ON resistance versus analog voltage. Positive analog

input voltage should be restricted to 4 volts less than V+ assur-

ing the switch remains open circuit in the OFF state. No in-

crease in switch ON resistance occurs when operating at supply

voltages less than ± 15 volts (see plot). Small signals have a 3 dB

down frequency of 70 MHz (see insertion loss versus frequency

plot).

ANALOG CURRENT

The analog switches in the ON state are JFETs biased in their

triode region and act as switches for analog current up to the IA

specification (see plot of IDS vs VDS). Some applications require

pulsed currents exceeding the IA spec. For example, an integra-

tor reset switch discharging a shunt capacitor will produce a

peak current of IA(PEAK) = VCAP/RDS(ON). In this application, it is

best to connect the source to the most positive end of the ca-

pacitor, thereby achieving the lowest switch resistance and

–10–

REV. A

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