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HCF4042BM1 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
View to exact match
HCF4042BM1
ST-Microelectronics
STMicroelectronics ST-Microelectronics
HCF4042BM1 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
HCF4042B
QUAD CLOCKED D LATCH
s CLOCK POLARITY CONTROL
s Q AND Q OUTPUTS
s COMMON CLOCK
s LOW POWER TTL COMPATIBLE
s STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s QUIESCENT CURRENT SPECIFIED UP TO
20V
s 5V, 10V AND 15V PARAMETRIC RATINGS
s INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
s 100% TESTED FOR QUIESCENT CURRENT
s MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4042B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4042B types contains four latch circuit,
each strobes by a common clock. Complementary
buffered outputs are available from each circuit.
The impedance of the n and p channel output
devices is balanced and all outputs are electrically
identical.
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF4042BEY
HCF4042BM1
T&R
HCF4042M013TR
Information present at the data input is transferred
to outputs Q and Q during the CLOCK level which
is programmed by the POLARITY input. For
POLARITY = 0 the transfer occurs during the 0
CLOCK level and for POLARITY = 1 the transfer
occurs during the 1 CLOCK level. The outputs
follow the data input providing the CLOCK and
POLARITY levels defined above are present.
When a CLOCK transition occurs (positive for
POLARITY = 0 and negative for POLARITY = 1)
the information present at the input during the
CLOCK transition is retained at the outputs until
an opposite CLOCK transition occurs.
PIN CONNECTION
September 2001
1/9
 

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