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74F125PC View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
74F125PC Quad Buffer (3-STATE) Fairchild
Fairchild Semiconductor Fairchild
74F125PC Datasheet PDF : 5 Pages
1 2 3 4 5
April 1988
Revised September 2000
74F125
Quad Buffer (3-STATE)
Features
s High impedance base inputs for reduced loading
Ordering Code:
Order Number Package Number
Package Description
74F125SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F125PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Unit Loading/Fan Out
Pin Names
Function Table
An, Bn
On
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
Description
Inputs
Outputs
U.L.
HIGH/LOW
Input IIH/IIL
Output IOH/IOL
1.0/0.033
20 µA/20 µA
600/106.6 (80) 12 mA/64 mA (48 mA)
Inputs
An
Bn
L
L
L
H
H
X
Output
O
L
H
Z
© 2000 Fairchild Semiconductor Corporation DS009475
www.fairchildsemi.com
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