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74LV257PWDH View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
74LV257PWDH Quad 2-input multiplexer (3-State) Philips
Philips Electronics Philips
74LV257PWDH Datasheet PDF : 12 Pages
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Philips Semiconductors
Quad 2-input multiplexer (3-State)
Product specification
74LV257
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
Non-inverting data path
Output capability: bus driver
ICC category: MSI
DESCRIPTION
The 74LV257 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT257.
The 74LV257 is a quad 2-input multiplexer with 3-state outputs, which
select 4 bits of data from two sources and are controlled by a common
data select input (S). The data inputs from source 0 (1l0 to 4l0) are
selected when input S is LOW and the data inputs from source 1 (1l1
to 4l1) are selected when S in HIGH. Data appears at the outputs (1Y
to 4Y) in true (non-inverting) from the selected inputs. The 74LV257 is
the logic implementation of a 4-pole, 2-position switch, where the
position of the switch is determined by the logic levels applied to S.
The outputs are forced to a high impedance OFF-state when OE is
HIGH.
The logic equations for the outputs are:
1Y = OE × (1l1 × S + 1l0 × S)
2Y = OE × (2l1 × S + 2l0 × S)
3Y = OE × (3l1 × S + 3l0 × S)
4Y = OE × (4l1 × S + 4l0 × S)
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
nl0, nl1 to nY
S to nY
CL = 15 pF;
VCC = 3.3 V
CI
Input capacitance
CPD
Power dissipation capacitance per gate
VI = GND to VCC1
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL × VCC2 × fo) = sum of the outputs.
TYPICAL
10
14
3.5
30
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV257 N
74LV257 D
74LV257 DB
74LV257 PW
NORTH AMERICA
74LV257 N
74LV257 D
74LV257 DB
74LV257PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
S1
1I0 2
1I1 3
IY 4
2l0 5
2l1 6
2Y 7
GND 8
16 VCC
15 OE
14 4l0
13 4l1
12 4Y
11 3l0
10 3l1
9 3Y
SV00636
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
S
Common data select input
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
1l0 to 4l0
1l1 to 4l1
1Y to 4Y
Data inputs from source 0
Data inputs from source 1
3-state multiplexer outputs
8
GND
Ground (0 V)
15
OE
3-State output enable input
(active LOW)
16
VCC
Positive supply voltage
1998 May 20
2
853-1985 19420
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