ADV7182 View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
ADV7182 Datasheet PDF : 96 Pages
| |||
ADV7182
1
PFTOGSIGN
0
ADVANCE TOGGLE OF
FIELD BY PFTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
YES
NO
PFTOGDELO
1
0
ADDITIONAL
DELAY BY
1 LINE
PFTOGDELE
0
1
ADDITIONAL
DELAY BY
1 LINE
FIELD
TOGGLE
Figure 41. PAL FIELD Toggle
PFTOGDELO, PAL FIELD Toggle Delay on Odd Field,
Address 0xEA[7]
When PFTOGDELO is 0 (default), there is no delay.
Setting PFTOGDELO to 1 delays the FIELD toggle/transition
by one line relative to PFTOG (odd field).
PFTOGDELE, PAL FIELD Toggle Delay on Even Field,
Address 0xEA[6]
When PFTOGDELE is 0, there is no delay.
Setting PFTOGDELE to 1 (default) delays the FIELD
toggle/transition by one line relative to PFTOG (even field).
PFTOGSIGN, PAL FIELD Toggle Sign, Address 0xEA[5]
Setting PFTOGSIGN to 0 delays the field transition and set to
low when manual programming.
Setting PFTOGSIGN to 1 (default) advances the field transition;
however, it is not suitable for user programming.
PFTOG, PAL FIELD Toggle, Address 0xEA[4:0]
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
For all NTSC/PAL field timing controls, the F bit in the AV
code and the FIELD signal are modified.
Data Sheet
SYNC PROCESSING
The ADV7182 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits: ENHSPLL and
ENVSPROC.
ENHSPLL, Enable HSYNC Processor, Address 0x01[6]
The HSYNC processor is designed to filter incoming HSYNCs that
have been corrupted by noise, providing improved performance
for video signals with stable time bases but poor SNR.
Setting ENHSPLL to 0 disables the HSYNC processor.
Setting ENHSPLL to 1 (default) enables the HSYNC processor.
ENVSPROC, Enable VSYNC Processor, Address 0x01[3]
This block provides extra filtering of the detected VSYNCs to
improve vertical lock.
Setting ENVSPROC to 0 disables the VSYNC processor.
Setting ENVSPROC to 1 (default) enables the VSYNC processor.
VBI DATA DECODE
The VBI data processor (VDP) on the ADV7182 can slice both
low bandwidth standards and high bandwidth standards such as
teletext.
The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in output 656 data stream. For low data rate VBI standards
like CC/WSS/CGMS, the decoded data bytes can be read from
the I2C registers.
The VBI data standards that can be decoded by the VDP are
listed in Table 73 and Table 74.
Table 73. PAL
Feature
Teletext System A, Teletext System C, or
Teletext System D
Teletext System B/ Teletext System WST
Wide Screen Signaling (WSS)
Closed Captioning (CCAP)
Standard
ITU-R BT.653
ITU-R BT.653
ITU-R BT.1119-1/
ETSI EN.300294
Not applicable
Table 74. NTSC
Feature
Teletext System B and Teletext System D
Teletext System C/ Teletext System NABTS
Copy Generation Management System (CGMS)
Closed Captioning (CCAP)
Standard
ITU-R BT.653
ITU-R BT.653/
EIA-516
EIA-J CPR-1204/
IEC 61880
EIA-608
Rev. A | Page 48 of 96
|
|
Share Link: 