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ADV7182 View Datasheet(PDF) - Analog Devices

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ADV7182 Datasheet PDF : 96 Pages
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ADV7182
VSYNC and FIELD Configuration
The following controls allow the user to configure the behavior of
the VSYNC and FIELD output signals, as well as the generation
of embedded AV codes. Note that the VSYNC and FIELD signals
can be output on the VS/FIELD/SFL pin or the HS pin (see the
Global Pin Control section).
NEWAVMODE, New AV Mode, Address 0x31[4]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit Analog Devices encoders. No adjustments are possible.
When NEWAVMODE is 1 (default), it enables the manual position
of the VSYNC, FIELD, and AV codes using Register 0x32 to
Register 0x33 and Register 0xE5 to Register 0xEA. Default register
settings are CCIR656 (BT.565-4) compliant; see Figure 32,
Figure 33 for NTSC and Figure 37, Figure 38 for PAL
HVSTIM, Horizontal VSYNC Timing, Address 0x31[3]
The HVSTIM bit allows the user to select where the VSYNC
signal is asserted within a line of video. Some interface circuitry
may require VSYNC to go low while HSYNC is low.
When HVSTIM is 0 (default), the start of the line is relative to HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
VSBHO, VSYNC Begin Horizontal Position Odd,
Address 0x32[7]
The VSBHO and VSBHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HSYNC is high or low.
When VSBHO is 0 (default), the VSYNC signal goes high in the
middle of a line of video (odd field).
When VSBHO is 1, the VSYNC signal changes state at the start
of a line (odd field).
VSBHE, VSYNC Begin Horizontal Position Even,
Address 0x32[6]
The VSBHO and VSBHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HS is high or low.
When VSBHE is 0 (default), the VSYNC signal goes high in the
middle of a line of video (even field).
When VSBHE is 1, the VSYNC signal changes state at the start
of a line (even field).
Data Sheet
VSEHO, VSYNC End Horizontal Position Odd,
Address 0x33[7]
The VSEHO and VSEHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HSYNC is high or low.
When VSEHO is 0 (default), the VSYNC signal goes low
(inactive) in the middle of a line of video (odd field).
When VSEHO is 1, the VSYNC signal changes state at the start
of a line (odd field).
VSEHE, VSYNC End Horizontal Position Even,
Address 0x33[6]
The VSEHO and VSEHE bits select the position within a line at
which the VSYNC signal (not the bit in the AV code) becomes
active. Some follow-on chips require the VSYNC signal to
change state only when HS is high or low.
When VSEHE is 0 (default), the VSYNC signal goes low
(inactive) in the middle of a line of video (even field).
When VSEHE is 1, the VSYNC signal changes state at the start
of a line (even field).
PVS, VSYNC Polarity, Address 0x37[5]
The polarity of the VSYNC signal can be inverted using the PVS
bit.
When PVS is 0 (default), VSYNC is active high.
When PVS is 1, VSYNC is active low.
PF, FIELD Polarity, Address 0x37[3]
The FIELD pin can be inverted using the PHS bit.
When PHS is 0 (default), FIELD pin is active high.
When PHS is 1, FIELD pin is active low.
Rev. A | Page 42 of 96
 

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