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74HC/HCT192 View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
74HC/HCT192 Presettable synchronous BCD decade up/down counter Philips
Philips Electronics Philips
74HC/HCT192 Datasheet PDF : 13 Pages
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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT192
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
min.
+25
typ. max.
74HC
40 to +85 40 to +125
min. max. min. max.
UNIT VCC
(V)
WAVEFORMS
tW
up clock pulse width
120 39
HIGH or LOW
24 14
20 11
150
180
30
36
26
31
ns 2.0 Fig.7
4.5
6.0
tW
down clock pulse width 140 50
HIGH or LOW
28 18
24 14
175
210
35
42
30
36
ns 2.0 Fig.7
4.5
6.0
tW
master reset pulse width 80 22
HIGH
16 8
14 6
100
120
20
24
17
20
ns 2.0 Fig.10
4.5
6.0
tW
parallel load pulse width 80 22
LOW
16 8
14 6
100
120
20
24
17
20
ns 2.0 Fig.9
4.5
6.0
trem
removal time
PL to CPU, CPD
50 3
10 1
91
65
75
13
15
11
13
ns 2.0 Fig.9
4.5
6.0
trem
removal time
MR to CPU, CPD
50 0
10 0
90
65
75
13
15
11
13
ns 2.0 Fig.10
4.5
6.0
tsu
set-up time
Dn to PL
80 22
16 8
14 6
100
120
20
24
17
20
ns 2.0 Fig.11 note:
4.5 CPU = CPD =
6.0 HIGH
th
hold time
Dn to PL
0 14
0
0
0 5
0
0
0 4
0
0
ns 2.0 Fig.11
4.5
6.0
th
hold time
CPU to CPD,
CPD to CPU
80 19
16 7
14 6
fmax
maximum up, down clock 4.0 12
pulse frequency
20 36
24 43
100
120
20
24
17
20
3.2
2.6
16
13
19
15
ns 2.0 Fig.13
4.5
6.0
MHz 2.0 Fig.7
4.5
6.0
December 1990
8
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