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NLV74HC4040ADR2G View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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NLV74HC4040ADR2G
ON-Semiconductor
ON Semiconductor ON-Semiconductor
NLV74HC4040ADR2G Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
MC74HC4040A
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negative−edge triggering clock input. A high−to−low
transition on this input advances the state of the counter.
Reset (Pin 11)
Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.
OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Active−high outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING WAVEFORMS
tf
tr
90%
VCC
Clock
50%
10%
GND
tw
1/fMAX
tPLH
tPHL
90%
Q1 50%
10%
tTLH
tTHL
Clock
Reset
Any Q
VCC
50%
GND
trec
tw
VCC
50%
GND
tPHL
50%
Figure 2.
Figure 3.
Qn
50%
tPLH
VCC
GND
tPHL
Qn+1
50%
Figure 4.
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
http://onsemi.com
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