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LB1823M View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
View to exact match
LB1823M Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
External Component Functions
LB1823M
Part
C1
C2
R1, C3
C4, C5, R2
C6, C7, R3, R4, R5
C8
C9, C10, R7, R8
R10
R11, R12
R13, R14, R15
R16
R17, R18, R19
R20
D1, D2, D3
Function
Power supply stabilization
IC power supply stabilization
PWM frequency setting
External crystal oscillator circuit
Servo constants
IC internal power supply
stabilization
Reset pulse generation
FG amplifier gain and frequency
characteristics settings
Limit current setting
Hall element bias current settings
Sink current settings
Shunt regulator bias current
settings
Pull-down resistors
Start time assurance
Regeneration current absorption
Description
Choose a value such that the voltage fluctuations due to the motor drive currents are
stabilized.
Attach as close as possible to pins 17 and 24.
Use a resistor of 30 kor larger for R1.
See the figure on page 6.
If the capacitance of this capacitor is too small, it will become harder to reset the internal IC
logic reliably and incorrect logic operation may occur. Attach as close as possible to pins 11
and 24.
Output current IOUT = VRF/R10
These resistors set the sink currents for the UL, VL and WL (open collector) outputs.
Select a value such that a current of over 1 mA flows in the VM voltage range for which
guaranteed correct operation is desired.
These resistors speed up the motor drive output transistor off times.
Include R20 in applications in which the start up time is a problem.
Use Schottky diodes for D1, D2 and D3.
Notes on LB1823M Operation and External Components
1. Speed control circuit
The LB1823M uses a speed discriminator circuit and a PLL circuit in combination for speed control. The speed
discriminator generates an error output once every two FG periods using a charge pump technique. The PLL circuit
generates a phase error output once every FG period, also using a charge pump technique. By using a speed
discriminator circuit and a PLL circuit together, the LB1823M can suppress speed variations better than earlier
systems that only used a speed discriminator for speed control when used with motors faced with large load
variations. Since the following formula determines the FG servo frequency, the motor speed is set by the number of
FG pulses and the crystal oscillator frequency.
fFG (servo) = fOSC/8192
fOSC: Crystal oscillator frequency
2. Direct PWM drive
This IC adopts a direct PWM drive technique to minimize power loss in the outputs. The output transistors are
always saturated when on, and the motor drive power is adjusted by changing the duty with which the outputs are on.
Since the upper side transistors switch the outputs, Schottky, fast recovery, or similar diodes must be inserted
between OUT and ground (diodes D1, D2 and D3). (This is because through currents will flow in the upper side
transistors at the instant they turn on if these diodes do not have a short reverse recovery time.) Ordinary rectifying
diodes can be used between OUT and VCC. Transistors with no parasitic diodes must be used for the output lower
side transistors. If these transistors include parasitic diodes, through currents will flow due to their reverse recovery
time, even if Schottky diodes are used for D1, D2 and D3.
3. Current limiter circuit
The current limiter circuit operates (to limit the peak current) at a current determined by the formula I = 0.5/Rf
(where Rf = R10). The limiting operation suppresses the current by reducing the on-duty. No phase compensation
capacitor is required.
No. 4696-7/11
 

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