LC72191 View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
View to exact match
LC72191 Datasheet PDF : 16 Pages
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LC72191, 72191M, 72191JM
No.
Control block/data
Description
Related data
• This data sets up the programmable divider.
D0 to D15 is a binary value with D15 as the MSB.
The position of the LSB is changed by DV and SP as listed in the table below.
Programmable divider
DV SP LSB
Divisor setting
Actual divisor
(1) data
D0 to D15
1*
01
D0 256 to 65536
D0 256 to 65536
Twice the set value
The set value
DV
SP
00
D4 4 to 4096
The set value
* don’t care
When D4 is the LSB, bits D0 to D3 are ignored.
• Data that determines the states of the output ports OUT0 to OUT6. O0 determines the
OUT0 pin output. However, note that when O0 is 0, OUT0 will output a high level, and when O0
is 1, OUT0 will output a low level. O1 to O6 function in the same manner.
Output port data
• These can be used for a wide range of purposes, including, for example, band switching
(2) O0 to O6
signals.
TB
• When the TB bit is set to 1, the O0 data is ignored and the OUT0 pin outputs an 8 Hz clock
time base signal.
• Since the output port states are undefined when power is first applied, transfer the control data
quickly.
• Data that determines the operation of the general-purpose counter. When CTEN is 0, the 20-bit
binary counter (the general-purpose counter) is reset and the HCTR and LCTR pins are pulled
General-purpose counter down to ground. When CTEN is set to 1, the general-purpose counter reset state is cleared and
SC
(3) initial data
the counter operates according to the SC bit (the general-purpose selection data). In this state,
SF
CTEN
the general-purpose counter will count either the HCTR or LCTR input signal.
GT
• Since the general-purpose counter is reset by setting CTEN to 0, the result of a count operation
must be sent to the controller while CTEN is still 1.
Reference frequency
(4) data
R0 to R3
• Data that selects one of the ten LC72191 reference frequencies or sets the LC72191 to
backup mode in which PLL operation is disabled.
R0 R1 R2 R3
0
0
0
0
Reference frequency (kHz)
100
0
0
0
1
50
0
0
1
0
25
0
0
1
1
25
0
1
0
0
12.5
0
1
0
1
6.25
0
1
1
0
3.125
0
1
1
1
3.125
1
0
0
0
10
1
0
0
1
9
1
0
1
0
5
1
0
1
1
1
1
1
0
0
1
1
0
1
PLL inhibit state*
1
1
1
0
1
1
1
1
Note: * PLL inhibit (backup mode)
The programmable divider block is turned off, both the FMIN and AMIN pins are pulled
down to ground, and the charge pump outputs go to the floating state.
Continued on next page.
No. 3985-8/16
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