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ADV478KP35 View Datasheet(PDF) - Analog Devices

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ADV478KP35 Datasheet PDF : 12 Pages
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ADV478/ADV471
The contents of the pixel read mask register, which may be ac-
cessed by the MPU at any time, are bit-wise logically ANDed
with the P0–P7 inputs. Bit D0 of the pixel read mask register
corresponds to pixel input P0. The addressed location provides
24 bits (18 bits for the ADV471) of color information to the
three D/A converters.
For additional information on Pixel Mask Register, see applica-
tion note “Animation Using the Pixel Read Mask Register of the
ADV47X Series of Video RAM-DACs” (Publication Number
E1316–15–10/89).
The SYNC and BLANK inputs, also latched on the rising edge
of CLOCK to maintain synchronization with the color data, add
appropriately weighted currents to the analog outputs, produc-
ing the specific output levels required for video applications, as
illustrated in Figures 3 and 4. Tables IV and V detail how the
SYNC and BLANK inputs modify the output levels.
The SETUP input is used to specify whether a 0 IRE (SETUP
= GND) or 7.5 IRE (SETUP = VAA) blanking pedestal is to be
used.
The analog outputs of the ADV478 and ADV471 are capable
of directly driving a 37.5 load, such as a doubly terminated
75 coaxial cable.
OBSOLETE Figure 4. Composite Video Output Waveform (SETUP = GND)
Table V. Video Output Truth Table (SETUP = GND)
Description
WHITE LEVEL
DATA
DATA-SYNC
BLACK LEVEL
BLACK-SYNC
BLANK LEVEL
SYNC LEVEL
IOUT (mA)l
26.67
data+8.05
data
8.05
0
8.05
0
SYNC
1
1
0
1
0
1
0
BLANK
1
1
1
1
1
0
0
DAC
Input Data
FFH
data
data
00H
00H
xxH
xxH
NOTE
1Typical with full-scale IOG= 26.67 mA, SETUP = GND.
External voltage or current reference adjusted for 26.67 mA full-scale output.
REV. B
–9–
 

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