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ADV471KP80 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV471KP80 CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs ADI
Analog Devices ADI
ADV471KP80 Datasheet PDF : 12 Pages
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ADV478/ADV471
ADV478 Data Bus Interface
On the ADV478, the 8/6 control input is used to specify whether
the MPU is reading and writing 8 bits (8/6 = logical one) or 6
bits (8/6 = logical zero) of color information each cycle.
For 8-bit operation, Do is the LSB and D7 is the MSB of color
data.
Frame Buffer Interface
The P0–P7 and OL0–OL3 inputs are used to address the color
palette RAM and overlay registers, as shown in Table III.
Table III. Pixel and Overlay Control Truth Table (Pixel Read
Mask Register = FFH)
For 6-bit operation (and also when using the ADV471), color
OL0–OL3 P0–P7 Addressed by Frame Buffer
data is contained on the lower six bits of the data bus, with D0
being the LSB and D5 the MSB of color data. When writing
0H
00H
Color Palette RAM Location 00H
color data, D6 and D7 are ignored. During color read cycles,
0H
01H
Color Palette RAM Location 01H
D6 and D7 will be a logical zero.
ADV471 Data Bus Interface
0H
FFH
Color Palette RAM Location FFH
OBSOLETE Color data is contained on the lower six bits of the data bus,
1H
with D0 being the LSB and D5 the MSB of color data. When
2H
writing color data, D6 and D7 are ignored. During color read
cycles, D6 and D7 will be a logical zero.
FH
XXH
XXH
XXH
Overlay Color 1
Overlay Color 2
Overlay Color 15
Fiqure 3. Composite Video Output Waveform (SETUP = VAA)
Table IV. Video Output Truth Table (SETUP= VAA)
Description
WHITE LEVEL
DATA
DATA-SYNC
BLACK LEVEL
BLACK-SYNC
BLANK LEVEL
SYNC LEVEL
IOUT (mA)1
26.67
data + 9.05
data + 1.44
9.05
1.44
7.62
0
SYNC
1
1
0
1
0
1
0
NOTES
1Typical with full-scale IOG = 26.67 mA, SETUP = VAA.
External voltage or current reference adjusted for 26.67 mA full-scale output.
BLANK
1
1
1
1
1
0
0
DAC
Input Data
FFH
data
data
00H
00H
xxH
xxH
–8–
REV. B
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