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ADV471KP80 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV471KP80 CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs ADI
Analog Devices ADI
ADV471KP80 Datasheet PDF : 12 Pages
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ADV478/ADV471
CIRCUIT DESCRIPTION
To read color data, the MPU loads the address register (select-
MPU Interface
ing RAM or overlay read mode) with the address of the color
As illustrated in the functional block diagram, the ADV478 and palette RAM location or overlay register to be read. The MPU
ADV471 support a standard MPU bus interface, allowing the
performs three successive read cycles (8 or 6 bits each of red,
MPU direct access to the color palette RAM and overlay color
green and blue), using RS0–RS2 to select either the color pal-
registers.
ette RAM or overlay registers. Following the blue read cycle,
The RS0–RS2 select inputs specify whether the MPU is access-
ing the address register, color palette RAM, overlay registers or
read mask register, as shown in Table I. The 8-bit address reg-
the address register increments to the next location which the
MPU may read by simply reading another sequence of red,
green and blue data.
ister is used to address the color palette RAM and overlay regis- When accessing the color palette RAM, the address register re-
ters, eliminating the requirement for external address multiplexers. sets to 00H following a blue read or write cycle to RAM loca-
To write color data, the MPU writes to the address register (se-
tion FFH. When accessing the overlay color registers, the
OBSOLETE lecting RAM or overlay write mode) with the address of the
color palette RAM location or overlay register to be modified.
The MPU performs three successive write cycles (8 or 6 bits
each of red, green and blue), using RS0–RS2 to select either
the color palette RAM or overlay registers. During the blue
write cycle, the three bytes of color information are concat-
enated into a 24-bit word (18-bit word for the ADV471) and
written to the location specified by the address register. The ad-
dress register then increments to the next location which the
MPU may modify by simply writing another sequence of red,
green and blue data.
Table I. Control Input Truth Table
RS2 RS1 RS0 Addressed by MPU
0
0
0
1
0
0
0
Address Register (RAM Write Mode)
1
Address Register (RAM Read Mode)
1
Color Palette RAM
address register increments following a blue read or write cycle.
However, while accessing the overlay color registers, the four
most significant bits of the address register (ADDR4-7) are ig-
nored.
The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM/overlay registers
and the color registers (R, G and B in the block diagram) are
synchronized by internal logic and occur in the period between
MPU accesses. As only one pixel clock cycle is required to
complete the transfer, the color palette RAM and overlay regis-
ters may be accessed at any time with no noticeable disturbance
on the display screen.
To keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
0
1
0
Pixel Read Mask Register
the address register, incremented following a blue read or write
1
0
1
1
1
0
1
1
0
1
l
0
Address Register (Overlay Write Mode)
Address Register (Overlay Read Mode)
Overlay Registers
Reserved
cycle (ADDR0–7), are accessible to the MPU and are used to
address color palette RAM locations and overlay registers, as
shown in Table II. ADDR0 is the LSB when the MPU is ac-
cessing the RAM or overlay registers. The MPU may read the
address register at any time without modifying its contents or
the existing read/write mode.
Figure 1 illustrates the MPU read/write timing.
Table II. Address Register (ADDR) Operation
Value
RS2 RS1 RS0
ADDRa,b (Counts Modulo 3)
ADDR0–7 (Counts Binary)
00
01
10
00H–FFH
0
0
1
XXXX 0000 1
0
1
XXXX 0001 1
0
1
XXXX 0010 1
0
1
XXXX 1111 1
0
1
Addressed By MPU
Red Value
Green Value
Blue Value
Color Palette RAM
Reserved
Overlay Color 1
Overlay Color 2
Overlay Color 15
REV. B
–7–
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