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ADV478 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV478 CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs ADI
Analog Devices ADI
ADV478 Datasheet PDF : 12 Pages
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ADV478/ADV471
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
Composite blank control input (TTL compatible). A logic zero drives the analog outputs to the blanking level as
illustrated in Tables IV and V. It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the
pixel and overlay inputs are ignored
SETUP
Setup control input. Used to specify either a 0 IRE (SETUP = GND) or 7.5 IRE (SETUP = VAA) blanking
pedestal.
SYNC
Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source
on the analog outputs (see Figures 3 and 4). SYNC does not override any other control or data input, as shown in
Tables IV and V; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge
OBSOLETE CLOCK
P0–P7
OL0–OL3
IOR, IOG, IOB
IREF
of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the P0–P7, OL0–OL3, SYNC, and BLANK
inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedi-
cated TTL buffer.
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. P0
is the LSB. Unused inputs should be connected to GND.
Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color informa-
tion, as illustrated in Table III. When accessing the overlay palette, the P0–P7 inputs are ignored. They are
latched on the rising edge of CLOCK. OL0 is the LSB. Unused inputs should be connected to GND.
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 coaxial cable (Figures 5 and 6).
Full-scale adjust control. Note that the IRE relationships in Figures 3 and 4 are maintained, regardless of the
full-scale output current.
When using an external voltage reference (Figure 5), a resistor (RSET) connected between this pin and GND
controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output
current on each output is:
RSET () = K × 1,000 × VREF (V)/IOUT (mA)
K is defined in the table below, along with corresponding RSET values for doubly terminated 75 loads.
When using an external current reference (Figure 6), the relationship between IREF and the full-scale output
current on each output is:
IREF (mA) = IOUT (mA)/K
Mode
6-Bit
8-Bit
6-Bit
8-Bit
Pedestal
7.5 IRE
7.5 IRE
0 IRE
0 IRE
K
3.170
3.195
3.000
3.025
RSET ()
147
147
147
147
COMP
VREF
OPA
VAA
GND
WR
Compensation pin. If an external voltage reference is used (Figure 5), this pin should be connected to OPA. If an
external current reference is used, this pin should be connected to IREF. A 0.1 µF ceramic capacitor must always be
used to bypass this pin to VAA.
Voltage reference input. If an external voltage reference is used (Figure 5), it must supply this input with a 1.2 V
(typical) reference. If an external current reference is used (Figure 6), this pin should be left floating, except for
the bypass capacitor. A 0.1 µF ceramic capacitor must always be used to decouple this input to VAA as shown in
Figures 5 and 6.
Reference amplifier output. If an external voltage reference is used (Figure 5), this pin must be connected to
COMP. When using an external current reference (Figure 6), this pin should be left floating.
Analog power. All VAA pins must be connected to the Analog Power Plane.
Analog ground. All GND pins must be connected to the Ground Plane.
Write control input (TTL compatible). D0–D7 data is latched on the rising edge of WR, and RS0–RS2 are
latched on the falling edge of WR during MPU write operations. See Figure 1.
REV. B
–5–
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