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ADV471KP80 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV471KP80 CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs ADI
Analog Devices ADI
ADV471KP80 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV478/ADV471
TIMING CHARACTERISTICS1 (VAA2 = +5 V, SETUP = 8/6 = VAA, VREF = 1.235 V. RSET = 147 . All Specifications TMIN to TMAX3.)
Parameter KP80 Version KP66 Version KP50 Version KP35 Version Units Conditions/Comments
fMAX
80
66
50
35
MHz Clock Rate
t1
10
10
10
10
ns min RS0–RS2 Setup Time
t2
10
10
10
10
ns min RS0–RS2 Hold Time
t3
5
5
5
5
ns min RD Asserted to Data Bus Driven
t4
40
40
40
40
ns max RD Asserted to Data Valid
t5
20
20
20
20
ns max RD Negated to Data Bus 3-Stated
t6
10
10
10
10
ns min Write Data Setup Time
t7
10
10
10
10
ns min Write Data Hold Time
t8
50
50
50
50
ns min RD, WR Pulse Width Low
OBSOLETE t9
6 × t12
t10
3
t11
3
t12
12.5
t13
4
t14
4
t15
30
t16
3
t174
13
t18
2
tPD
4 × t12
6 × t12
3
3
15.3
5
5
30
3
15.3
2
4 × t12
6 × t12
3
3
20
6
6
30
3
20
2
4 × t12
6 × t12
3
3
28
7
9
30
3
28
2
4 × t12
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns typ
ns max
ns min
RD, WR Pulse Width High
Pixel and Control Setup Time
Pixel and Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay
NOTES
1TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load 10 pF, 37.5 . D0–D7 output load 50 pF. See timing notes in Figure 2.
2± 5% for 80 MHz and 66 MHz parts; ± 5% for 50 MHz and 35 MHz parts.
3Temperature Range (TMIN to TMAX); 0°C to +70°C.
4Settling time does not include clock and data feedthrough. For this test, the digital inputs have a 1 k resistor to ground and are driven by 74HC logic.
Specifications subject to change without notice
TIMING DIAGRAMS
Figure 1. MPU Read/Write Timing
REV. B
Figure 2. Video Input/Output Timing
–3–
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