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LM12454CIV-2006 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
LM12454CIV(2006) 12-Bit + Sign Data Acquisition System with Self-Calibration National-Semiconductor
National ->Texas Instruments National-Semiconductor
LM12454CIV Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Digital Characteristics (Notes 6, 7)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
VIN(1)
VIN(0)
IIN(1)
IIN(0)
CIN
VOUT(1)
VOUT(0)
IOUT
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
D0–D15 Input Capacitance
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE® Output Leakage Current
VA+ = VD+ = 5.5V
VA+ = VD+ = 4.5V
VIN = 5V
VIN = 0V
VA+ = VD+ = 4.5V
IOUT = −360 µA
IOUT = −10 µA
VA+ = VD+ = 4.5V
IOUT = 1.6 mA
VOUT = 0V
VOUT = 5V
0.005
−0.005
6
−0.01
0.01
2.0
V (min)
0.8
V (max)
1.0
µA (max)
−1.0
µA (max)
pF
2.4
V (min)
4.25
V (min)
0.4
V (max)
−3.0
µA (max)
3.0
µA (max)
Digital Timing Characteristics (Notes 6, 7, 8)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, tr = tf = 3 ns, and CL = 100
pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25˚C.
Symbol (See Figures
8, 9, 10)
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
CS or Address Valid to ALE Low Set-Up
1, 3
Time
40
ns (min)
CS or Address Valid to ALE Low Hold
2, 4
Time
20
ns (min)
5
ALE Pulse Width
45
ns (min)
6
RD High to Next ALE High
35
ns (min)
7
ALE Low to RD Low
20
ns (min)
8
RD Pulse Width
100
ns (min)
9
RD High to Next RD or WR Low
100
ns (min)
10
ALE Low to WR Low
20
ns (min)
11
WR Pulse Width
60
ns (min)
12
WR High to Next ALE High
75
ns (min)
13
WR High to Next RD or WR Low
140
ns (min)
14
Data Valid to WR High Set-Up Time
40
ns (min)
15
Data Valid to WR High Hold Time
30
ns (min)
16
RD Low to Data Bus Out of TRI-STATE
10
ns (min)
40
70
ns (max)
17
RD High to TRI-STATE
10
ns (min)
RL = 1 k
30
110
ns (max)
18
RD Low to Data Valid (Access Time)
10
ns (min)
30
80
ns (max)
20
Address Valid or CS Low to RD Low
20
ns (min)
21
Address Valid or CS Low to WR Low
20
ns (min)
19
Address Invalid from RD or WR High
10
ns (min)
22
INT High from RD Low
10
ns (min)
30
60
ns (max)
23
DMARQ Low from RD Low
10
ns (min)
30
60
ns (max)
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