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LM12454CIV-2006 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
LM12454CIV(2006) 12-Bit + Sign Data Acquisition System with Self-Calibration National-Semiconductor
National ->Texas Instruments National-Semiconductor
LM12454CIV Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Converter Characteristics (Notes 6, 7, 8, 9) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25, source impedance for
VREF+ and VREF− 25, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 10) (Note 11)
Units
DNL
8-Bit + Sign and “Watchdog” Mode
Differential Non-Linearity
±3/4
LSB (max)
8-Bit + Sign and “Watchdog” Mode
Zero Error
After Auto-Zero
±1/2
LSB (max)
8-Bit + Sign and “Watchdog” Full-Scale
Error
±1/2
LSB (max)
8-Bit + Sign and “Watchdog” Mode
DC Common Mode Error
±1/8
LSB
Multiplexer Channel-to-Channel
Matching
±0.05
LSB
VIN+
VIN−
VIN+ − VIN−
PSS
Non-Inverting Input Range
Inverting Input Range
Differential Input Voltage Range
Common Mode Input Voltage Range
Power Supply
Sensitivity (Note
15)
Zero Error
Full-Scale Error
Linearity Error
VA+ = VD+ = 5V ±10%
VREF+ = 4.5V, VREF− = GND
±0.2
±0.4
±0.2
GND
VA+
GND
VA+
−VA+
VA+
GND
VA+
±1.75
±2
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
LSB (max)
LSB (max)
LSB
CREF
CIN
VREF+/VREF− Input Capacitance
Selected Multiplexer Channel Input
Capacitance
85
pF
75
pF
Converter AC Characteristics (Notes 6, 7, 8, 9)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25, source impedance for
VREF+ and VREF− 25, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits (Note 11)
Units
%
Clock Duty Cycle
50
40
% (min)
60
% (max)
tC
Conversion Time
13-Bit Resolution, Sequencer
State S5 (Figure 15)
9-Bit Resolution, Sequencer State
S5 (Figure 15)
44 (tCLK)
21 (tCLK)
44 (tCLK) + 50 ns
21 (tCLK) + 50 ns
(max)
(max)
tA
Acquisition Time
Sequencer State S7 (Figure 15)
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and
“Watchdog” mode
9 (tCLK)
2 (tCLK)
9 (tCLK) + 50 ns
2 (tCLK) + 50 ns
(max)
(max)
tZ
Auto-Zero Time
Sequencer State S2 (Figure 15)
76 (tCLK)
76 (tCLK) + 50 ns
(max)
tCAL
Full Calibration Time
Sequencer State S2 (Figure 15) 4944 (tCLK) 4944 (tCLK) + 50 ns
(max)
Throughput Rate (Note 18)
LM12H458
89
88
kHz (min)
142
140
kHz (min)
5
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