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LM12454CIV-2006 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
LM12454CIV(2006) 12-Bit + Sign Data Acquisition System with Self-Calibration National-Semiconductor
National ->Texas Instruments National-Semiconductor
LM12454CIV Datasheet PDF : 36 Pages
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2.0 Internal User-Programmable Registers (Continued)
A4 A3 A2 A1 A0 Purpose Type D7
D6
D5
D4
D3
D2
D1 D0
000
0
to
0
Instruction
R/W
111
000
RAM
(RAM
Pointer =
0
to
1
00)
R/W
111
VIN− (MUXOUT−)
(Note 21)
Acquisition Time
VIN+ (MUXOUT+)
(Note 21)
Pause Loop
Watch-
8/12 Timer Sync
dog
000
Instruction RAM R/W
0
to
0 (RAM Pointer =
111
01)
R/W
Comparison Limit #1
Don’t Care
>/< Sign
000
0
to
1
R/W
Don’t Care
>/< Sign
111
000
0
to
0
Instruction
R/W
111
000
RAM
(RAM
Pointer =
0
to
1
10)
R/W
111
Comparison Limit #2
Don’t Care
>/< Sign
Chan Stand-
Auto-
10000
R/W I/O Sel Auto Zeroec Mask
Full Cal
Reset Start
by
Zero
Configuration
DIAG
Register
Test =
10001
R/W
Don’t Care
(Note
RAM Pointer
0
22)
10010
Interrupt
R/W INT7
INT6
INT5 INT4 INT3 INT2 INT1 INT0
10011
Enable
Register
R/W Number of Conversions in Conversion FIFO to Sequencer Address to
Generate INT2
Generate INT1
10100
10101
Interrupt
Status
Register
R INST7 INST6 INST5 INST4 INST3 INST2 INST1 INST0
Address of Sequencer
Actual Number of Conversions Results in
R
Instruction being
Conversion FIFO
Executed
10110
Timer
R/W
Timer Preset: Low Byte
10111
Register
R/W
Timer Preset: High Byte
1 1 0 0 0 Conversion
R
Conversion Data: LSBs
11001
FIFO
R
Address or Sign
Sign
Conversion Data: MSBs
1 1 0 1 0 Limit Status
R
Limit #1 Status
11011
Register
R
Limit #2 Status
FIGURE 14. LM12(H)454/8 Memory Map for 8-Bit Wide Data Bus (BW = “1” and Test Bit = “0”)
Note 21: LM12454 (Refer toTable 2).
Note 22: LM12(H)458 only. Must be set to “0” for the LM12454.
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