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MC14040BD View Datasheet(PDF) - Motorola => Freescale

Part Name
Description
View to exact match
MC14040BD
Motorola
Motorola => Freescale Motorola
MC14040BD Datasheet PDF : 6 Pages
1 2 3 4 5 6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14038B
See Page 6-92
MC14040B
12-Bit Binary Counter
The MC14040B 12–stage binary counter is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping circuit
and 12 stages of ripple–carry binary counter. The device advances the count
on the negative–going edge of the clock pulse. Applications include time
delay circuits, counter controls, and frequency–driving circuits.
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Common Reset Line
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Pin–for–Pin Replacement for CD4040B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD DCSupplyVoltage
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ lin, lout Input or Output Current (DC or Transient),
± 10
mA
per Pin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation, per Package†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
_C
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
TRUTH TABLE
Clock
X
Reset
0
0
1
Output State
No Change
Advance to next state
All Outputs are low
X = Don’t Care
CLOCK
10
RESET
11
LOGIC DIAGRAM
Q1
Q2
Q3
9
7
6
CQ
CQ
CQ
CQ
R
CQ
R
CQ
R
Q10
Q11
Q12
14
15
1
CQ
CQ
CQ
CQ
CQ
C
R
R
R
Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2
Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12
VDD = PIN 16
VSS = PIN 8
REV 3
1/94
©MMCot1or4o0la4, I0nBc. 1995
150
MOTOROLA CMOS LOGIC DATA
 

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