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T8110-BAL-DB View Datasheet(PDF) - Agere -> LSI Corporation

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T8110-BAL-DB Datasheet PDF : 222 Pages
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Data Sheet
May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch
and Packet Payload Engine
6 Operating Control and Status (continued)
n Soft reset 4: Reset the interrupt in-service register only.
n RESET_PENDING_MEM: Reset the virtual channel NOTIFY_PENDING memory.
n RESET_QUEUE: Reset the virtual channel NOTIFY_QUEUE FIFO.
Table 22. Reset Registers
Byte
Address
Name Bit(s) Mnemonic
Value
Function
0x00100 Soft Reset 7:0 SRESR 0000 0000 NOP (default value).
0000 0001 Reset all registers and connection valid flags.
0000 0010 Reset all registers.
0001 0000 Reset interrupt pending and in-service registers.
0010 0000 Reset interrupt in-service register only.
0100 0000 Reset virtual channel NOTIFY_PENDING memory.
1000 0000 Reset virtual channel NOTIFY_QUEUE.
0x00101 Reset Select 7:4 Reserved
3
PMBEB
2
PRBEB
1
HRBEB
0
SRBEB
0000
0
1
0
1
0
1
0
1
NOP (default).
Disable PCI reset to minibridge (default).
Enable PCI reset to minibridge.
Disable PCI reset to back end (default).
Enable PCI reset to back end.
Disable hard reset to back end.
Enable hard reset to back end (default).
Disable soft resets to back end.
Enable soft resets to back end (default).
6.1.2 Master Output Enable Register
The master output enable register is used to control master output enables to various groups of T8110 signals,
including the following:
L-bus data streams (L_D[31:0])
L-bus clocks (L_SC[3:0], FG[7:0] when used as frame group outputs)
H-bus data streams (CT_D[31:0])
H-bus clocks (CT_C8_A, /CT_FRAME_A, CT_C8_B, /CT_FRAME_B, CT_NETREF1,CT_NETREF2, /C16+,
/C16–, /C4, C2, SCLK, /SCLKx2, /FR_COMP)
GPIO (GP[7:0])
FGIO (FG[7:0] when used as programmable register outputs)
Minibridge (MB_A[15:0], MB_CS[7:0], MB_RD, MB_WR, MB_D[15:0])
T8110 outputs that are not programmatically enabled (i.e., always driven except during reset) include the following:
CLKERR, SYSERR, PRI_REF_OUT, NR1_SEL_OUT, and NR2_SEL_OUT.
Agere Systems Inc.
47
 

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