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T8110-BAL-DB View Datasheet(PDF) - Agere -> LSI Corporation

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T8110-BAL-DB Datasheet PDF : 222 Pages
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Ambassador T8110 PCI-Based H.100/H.110 Switch
and Packet Payload Engine
Data Sheet
May 2001
4 PCI Interface (continued)
Table 11. PCI Interface Registers Map (continued)
DWORD Section
Address Cross
(20 bits) Reference
Byte 3
Registers
Byte 2
Byte 1
Byte 0
0x00400
8.1
FG0 rate
FG0 width
FG0 upper start
FG0 lower start
0x00410
8.1
FG1 rate
FG1 width
FG1 upper start
FG1 lower start
0x00420
8.1
FG2 rate
FG2 width
FG2 upper start
FG2 lower start
0x00430
8.1
FG3 rate
FG3 width
FG3 upper start
FG3 lower start
0x00440
8.1
FG4 rate
FG4 width
FG4 upper start
FG4 lower start
0x00450
8.1
FG5 rate
FG5 width
FG5 upper start
FG5 lower start
0x00460
8.1
FG6 rate
FG6 width
FG6 upper start
FG6 lower start
0x00470
8.1
FG7 rate
FG7 width
FG7 upper start
FG7 lower start
0x00474
8.2
FG7 mode upper
FG7 mode lower FG7 counter high FG7 counter low byte
byte
0x00480
8.3
Reserved
FGIO R/W
FGIO read mask FGIO data register
0x00500
9.1
GPIO override
GPIO R/W
GPIO read mask GPIO data register
0x00600 12.1
FGIO interrupt polarity
Reserved
FGIO interrupt
enable
FGIO interrupt
pending
0x00604 12.1 GPIO interrupt polarity
Reserved
GPIO interrupt
enable
GPIO interrupt
pending
0x00608
12.1
System interrupt enable, System interrupt
upper
enable, lower
System interrupt
pending, upper
System interrupt
pending, lower
0x0060C 12.1
Clock interrupt enable,
upper
Clock interrupt
enable, lower
Clock interrupt
pending, upper
Clock interrupt
pending, lower
0x00610 12.1
CLKERR output select SYSERR output
select
PCI_INTA output
select
Arbitration control
0x00614 12.1
CLKERR pulse width
SYSERR pulse
width
Reserved
Reserved
0x006FC 12.1
In-service, byte 3
In-service, byte 2 In-service, byte 1 In-service, byte 0
0x00700 11.1 CS0 address setup wait CS0 read hold wait CS0 read width wait CS0 read setup wait
0x00704 11.1
CS0 address hold wait CS0 write hold wait CS0 write width wait CS0 write setup wait
0x00710 11.1 CS1 address setup wait CS1 read hold wait CS1 read width wait CS1 read setup wait
0x00714 11.1
CS1 address hold wait CS1 write hold wait CS1 write width wait CS1 write setup wait
0x00720 11.1 CS2 address setup wait CS2 read hold wait CS2 read width wait CS2 read setup wait
0x00724 11.1
CS2 address hold wait CS2 write hold wait CS2 write width wait CS2 write setup wait
0x00730 11.1 CS3 address setup wait CS3 read hold wait CS3 read width wait CS3 read setup wait
0x00734 11.1
CS3 address hold wait CS3 write hold wait CS3 write width wait CS3 write setup wait
0x00740 11.1 CS4 address setup wait CS4 read hold wait CS4 read width wait CS4 read setup wait
0x00744 11.1
CS4 address hold wait CS4 write hold wait CS4 write width wait CS4 write setup wait
0x00750 11.1 CS5 address setup wait CS5 read hold wait CS5 read width wait CS5 read setup wait
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