T8110-BAL-DB View Datasheet(PDF) - Agere -> LSI Corporation

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Description

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T8110-BAL-DB

Ambassador® T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine

Agere -> LSI Corporation 

Ambassador T8110 PCI-Based H.100/H.110 Switch

and Packet Payload Engine

Data Sheet

May 2001

2 Pin Description (continued)

2.3 Special Buffer Requirements

2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down

The H1x0 bus pins require special consideration for H.100 and H.110 usage. There are two control pins to select

between various internal bus pull-ups/pull-downs, as shown below:

n H100_ENABLE. Enables internal 50 kΩ pull-ups on CT_Dn, CT_NETREF1, CT_NETREF2, CT_C8_A,

CT_C8_B, /CT_FRAME_A, and /CT_FRAME_B signals.

n H110_ENABLE. Enables internal 20 kΩ pull-downs on all 32 CT_Dn signals, CT_NETREF1, and CT_NETREF2

to the VPRECHARGE signal.

Note: The two H1x0 enables are active-high. Only one or the other should ever be asserted.

Warning: Do not assert both at the same time.

Please refer to Figure 2 for more detail.

CT_Dn, CT_NETREF1, CT_NETREF2

TO OTHER

CT_Dn

VDD

50 kΩ, MIN

20 kΩ, MIN

PAD

APPLY 0.7 V, NOMINAL

PAD VPRECHARGE

PAD H100_ENABLE

PAD H110_ENABLE

VDD

50 kΩ, MIN

PAD

CT_C8_A, CT_C8_B,

/CT_FRAME_A, /CT_FRAME_B

5-9611 (F)

Figure 2. T8110 Pull-Up/Pull-Down Arrangement for H1x0 Pins

2.3.2 Local Bus Signal Internal Pull-Up

The LPUE input is active-high; and is used to activate pull-ups on the following local signals: GP[7:0], FG[7:0],

MB_D[15:0], LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.

18

Agere Systems Inc.

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