Ambassador T8110 PCI-Based H.100/H.110 Switch
and Packet Payload Engine
Data Sheet
May 2001
2 Pin Description (continued)
Table 9. T8110 Pinouts (continued)
Ball
Pin Name
B20
XTAL1_IN
C19
XTAL1_OUT
E20
XTAL2_IN
F19
XTAL2_OUT
A15
LREF0
B15
LREF1
C15
LREF2
C16
LREF3
A16
LREF4
B16
LREF5
B17
LREF6
C17
LREF7
G20
TCLK_OUT
A17
PRI_REF_OUT
A18
PRI_REF_IN
B18
NR1_SEL_OUT
A19
NR1_DIV_IN
D19
NR2_SEL_OUT
C20
NR2_DIV_IN
D1
GP0/AMASTER
E1
GP1/BMASTER
E2
GP2/FWD_PCIRST#
F2
GP3
D3
GP4
F3
GP5
E3
GP6
E4
GP7
Y1
RESET#
V3
SYSERR
W2
CLKERR
J17
LPUE
G4
EE_CS
U5
VIO/µP_SELECT
C18
TRST#
E18
TCK
D18
TMS
F18
TDI
G18
TDO
Clock Circuit Interface
Buffer Type
Pull Up/Down (see note on page 11)
Input
Crystal feedback
Input
Crystal feedback
Input-Schmitt
Input-Schmitt
Input-Schmitt
Input-Schmitt
Input-Schmitt
Input-Schmitt
Input-Schmitt
Input-Schmitt
8 mA 3-state
8 mA 3-state
Input-Schmitt
8 mA 3-state
Input-Schmitt
8 mA 3-state
Input-Schmitt
GPIO Interface
—
—
—
—
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
—
—
LPUE: 50 kΩ up
—
LPUE: 50 kΩ up
—
LPUE: 50 kΩ up
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
8 mA I/O-Schmitt
Miscellaneous Interfaces
Input-Schmitt
8 mA 3-state
8 mA 3-state
Input
8 mA 3-state
—
JTAG Interface
Input-Schmitt
Input-Schmitt
Input-Schmitt
Input-Schmitt
4 mA 3-state
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
LPUE: 50 kΩ up
50 kΩ up
—
—
50 kΩ up
—
20 kΩ down
50 kΩ up
50 kΩ up
50 kΩ up
50 kΩ up
—
16
Agere Systems Inc.