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FW82371AB View Datasheet(PDF) - Intel

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FW82371AB Datasheet PDF : 284 Pages
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E
82371AB (PIIX4)
Name
SMEMW#
ZEROWS#
Type
Description
O STANDARD MEMORY WRITE. PIIX4 asserts SMEMW# to request an ISA memory
slave to accept data from the data lines. If the access is below the 1-Mbyte range
(00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA master
cycles, PIIX4 asserts SMEMW#. SMEMW# is a delayed version of MEMW#.
During Reset: High-Z After Reset: High
During POS: High
I ZERO WAIT STATES. An ISA slave asserts ZEROWS# after its address and
command signals have been decoded to indicate that the current cycle can be
shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An 8-bit
memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect
during 16-bit I/O cycles.
If IOCHRDY is negated and ZEROWS# is asserted during the same clock, then
ZEROWS# is ignored and wait states are added as a function of IOCHRDY.
2.1.3. X-BUS INTERFACE
Name
A20GATE
BIOSCS#
KBCCS#/
GPO26
MCCS#
PCS0#
PCS1#
RCIN#
Type
Description
I ADDRESS 20 GATE. This input from the keyboard controller is logically combined with
bit 1 (FAST_A20) of the Port 92 Register, which is then output via the A20M# signal.
O BIOS CHIP SELECT. This chip select is driven active during read or write accesses to
enabled BIOS memory ranges. BIOSCS# is driven combinatorially from the ISA
addresses SA[16:0] and LA[23:17], except during DMA cycles. During DMA cycles,
BIOSCS# is not generated.
During Reset: High
After Reset: High
During POS: High
O KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O read or
write accesses to KBC locations 60h and 64h. It is driven combinatorially from the ISA
addresses SA[19:0] and LA[23:17].
If the keyboard controller does not require a separate chip select, this signal can be
programmed to a general purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
O MICROCONTROLLER CHIP SELECT. MCCS# is asserted during I/O read or write
accesses to IO locations 62h and 66h. It is driven combinatorially from the ISA
addresses SA[19:0] and LA[23:17].
During Reset: High
After Reset: High
During POS: High
O PROGRAMMABLE CHIP SELECTS. These active low chip selects are asserted for
ISA I/O cycles which are generated by PCI masters and which hit the programmable
I/O ranges defined in the Power Management section. The X-Bus buffer signals (XOE#
and XDIR#) are enabled while the chip select is active. (i.e., it is assumed that the
peripheral which is selected via this pin resides on the X-Bus.)
During Reset: High
After Reset: High
During POS: High
I RESET CPU. This signal from the keyboard controller is used to generate an INIT
signal to the CPU.
PRELIMINARY
21
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
 

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