datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

MTV030N View Datasheet(PDF) - Myson Century Inc

Part Name
Description
View to exact match
MTV030N Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MYSON
TECHNOLOGY
MTV030
In the I2C read mode, 10 bytes of auto sizing video measurement data will be output directly from byte 0 to
byte 9 and continues with dummy data until stop condition occurred when I2C R/W bit is set to “1”.
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to
increase transmission efficiency. The row and column address will be incremented automatically when the for-
mat (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy
data.
TABLE 1. The configuration of transmission formats.
Address b7 b6 b5 b4 b3 b2 b1 b0 Format
Row
1 0 0 R4 R3 R2 R1 R0
Address Bytes Columnab 0
of Display Reg. Columnc 0
0 D8 C4 C3 C2 C1 C0
1 D8 C4 C3 C2 C1 C0
Data
D7 D6 D5 D4 D3 D2 D1 D0
Row
1 0 1 R4 R3 R2 R1 R0
Attribute Bytes Columnab 0 0 x C4 C3 C2 C1 C0
of Display Reg. Columnc 0 1 x C4 C3 C2 C1 C0
Data
D7 D6 D5 D4 D3 D2 D1 D0
a,b,c
a,b
c
a,b,c
a,b,c
a,b
c
a,b,c
There are 2 types of data should be accessed through the serial data interface, one is ADDRESS bytes of dis-
play registers, and other is ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5
of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column
addresses when transferring data from external controller. The bit6 of column address is used to differentiate
the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is
used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at
address bytes, bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB (bit7~bit0) of dis-
play fonts address to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be dis-
played at the same time. See Table 1. And for format (c), since D8 is filled while program column address of
address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
column address of address bytes again.
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure 3.
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
5/21
MTV030 Revision 1.0 10/15/1999
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]