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MTV118N24 View Datasheet(PDF) - Myson Century Inc

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MTV118N24
Myson
Myson Century Inc Myson
MTV118N24 Datasheet PDF : 30 Pages
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MYSON
TECHNOLOGY
MTV118
The vertical display center for a full-screen display may be figured out according to the information of
the vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the lead-
ing edge of VFLB is calculated using the following equation:
Vertical delay time = ( VERTD * 4 + 1 ) * H
Where H = 1 horizontal line display time
TABLE 2. Repeat Line Weight of Character
CH6-CH0
CH6,CH5=11
CH6,CH5=10
CH6,CH5=0x
CH4=1
CH3=1
CH2=1
CH1=1
CH0=1
Repeat Line Weight
+18*3
+18*2
+18
+16
+8
+4
+2
+1
TABLE 3. Repeat Line Number of Character
Repeater Line
Repeat Line #
Weight
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+1
- - - - - - - -v- - - - - - - - -
+2
- - - -v- - - - - - -v- - - - -
+4
- -v- - -v- - -v- - -v- - -
+8
-v-v-v-v-v-v-v-v- -
+16
- vvvvvvvvvvvvvvvv -
+17
vvvvvvvvvvvvvvvvv -
+18
vvvvvvvvvvvvvvvvvv
Note: ā€œvā€ means the nth line in the character would be repeated once, while ā€œ-ā€ means the nth line in the
character would not be repeated.
3.4 Horizontal Display Control
The horizontal display control is used to generate control timing for a horizontal display based on dou-
ble character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal dis-
play line includes 360 dots for 30 display characters and the remaining dots for a blank region. The
horizontal delay starting from the HFLB leading edge is calculated using the following equation:
Horizontal delay time = ( HORD * 6 + 49) * P
Where P = 1 XIN pixel display time
3.5 Display & Row Control Registers
The internal RAM contains display and row control registers. The display registers have 450 locations
which are allocated between row 0/column 0 and row 14/column 29 as shown in Figure 4. Each display
register has its corresponding character address on the address byte, and 1 blink bit and its corre-
sponding color bits on attribute bytes. The row control register is allocated at column 30 for row 0 to row
14; it is used to set character size for each respective row. If the double width character (CWS) is cho-
6/15
MTV118 Revision 2.0 01/01/1999
 

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