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SN74LS373 データシートの表示(PDF) - ON Semiconductor

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SN74LS373 Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT ON-Semiconductor
ON Semiconductor ON-Semiconductor
SN74LS373 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
SN74LS373, SN74LS374
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
LS373
LS374
Symbol
Parameter
Min Typ Max Min Typ Max Unit
Test Conditions
fMAX
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay,
Data to Output
Clock or Enable
to Output
35 50
MHz
12 18
12 18
ns
20 30
18 30
15 28
19 28
ns
CL = 45 pF,
RL = 667
tPZH
tPZL
Output Enable Time
15 28
25 36
20 28
21 28
ns
tPHZ
tPLZ
Output Disable Time
12 20
15 25
12 20
15 25
ns
CL = 5.0 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
LS373
LS374
Symbol
Parameter
Min
Max
Min
Max
Unit
tW
Clock Pulse Width
ts
Setup Time
th
Hold Time
15
15
ns
5.0
20
ns
20
0
ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
SN74LS373
AC WAVEFORMS
LE
Dn
OUTPUT
tW
tW
1.3 V
ts
th
tPLH
Figure 1.
OE
tPZL
VOUT
1.3 V
1.3 V
Figure 2.
1.3 V
tPLZ
1.3 V
VOL
0.5 V
tPHL
OE
tPZH
VOUT
1.3 V
tPHZ
1.3 V
Figure 3.
1.3 V
VOH
1.3 V
0.5 V
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