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74ABT16652CMTD View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74ABT16652CMTD
Fairchild
Fairchild Semiconductor Fairchild
74ABT16652CMTD Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Extended AC Electrical Characteristics
(SSOP Package)
TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
16 Outputs Switching
CL = 250 pF
1 Output Switching
CL = 250 pF
16 Outputs Switching
Units
(Note 8)
(Note 9)
(Note 10)
Min
Max
Min
Max
Min
Max
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Progagation Delay
Clock to Bus
Progagation Delay
Bus to Bus
Progagation Delay
SBA or SAB to
An or Bn
Output Enable Time
OEBAn or OEABn to
An or Bn
Output Disable Time
OEBA or OEAB to
1.5
5.8
2.0
7.5
2.5
10.0
ns
1.5
5.8
2.0
7.5
2.5
10.0
1.5
6.5
2.0
7.0
2.5
9.5
ns
1.5
6.5
2.0
7.0
2.5
9.5
1.5
6.0
2.0
7.5
2.5
10.0
1.5
6.0
2.0
7.5
2.5
10.0
ns
1.5
6.0
2.0
8.0
2.5
10.5
1.5
6.0
2.0
8.0
2.5
10.5
ns
1.5
6.0
1.5
6.0
(Note 11)
(Note 11)
ns
An or Bn
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay times are dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Skew (Note 12)
(SSOP Package)
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
16 Outputs Switching
CL = 250 pF
16 Outputs Switching
Units
(Note 12)
(Note 13)
Max
Max
tOSHL
(Note 14)
Pin to Pin Skew
HL Transitions
2.0
2.5
ns
tOSLH
(Note 14)
Pin to Pin Skew
LH Transitions
2.0
2.5
ns
tPS
(Note 15)
Duty Cycle
LH–HL Skew
2.0
2.5
tOST
(Note 14)
Pin to Pin Skew
LH/HL Transitions
2.8
3.0
ns
tPV
Device to Device Skew
3.5
4.0
ns
(Note 16)
LH/HL Transitions
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to
LOW (tOST). This specification is guaranteed but not tested.
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
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