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DM74AS652WM View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
DM74AS652WM
Fairchild
Fairchild Semiconductor Fairchild
DM74AS652WM Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Connection Diagram
Function Table
INPUTS
DATA I/O (Note 1)
OPERATION OR FUNCTION
GAB GBA CAB CBA SAB SBA
L H H or L H or L X
X
LH
X
X
A1
THRU
A8
Input
B1
THRU
B8
Input
DM74AS651
Isolation
Store A and B Data
DM74AS652
Isolation
Store A and B Data
LL X
X
X
L
Output
L L X H or L X
H
Input
Real Time B Data to A
Bus
Stored B Data to A Bus
Real Time B Data to A
Bus
Stored B Data to A Bus
HH X
X
L
X
H H H or L X
H
X
Input
Output
Real Time A Data to B
Bus
Stored A Data to B Bus
Real Time A Data to B
Bus
Stored A Data to B Bus
Stored A Data to B Bus Stored A Data to B Bus
H L H or L H or L H
H
Output
Output
& Stored B Data to A Bus & Stored B Data to A Bus
X H H or L X
X
Input
Unspecified Store A, Hold B
(Note 1)
Store A, Hold B
HH
X
X
(Note
2)
Input
Output Store A in both registers Store A in both registers
L X H or L
X
X Unspecified Input Hold A, Store B
(Note 1)
Hold A, Store B
LL
X
X
Output
(Note
2)
Input Store B in both registers Store B in both registers
H = HIGH Level
L = LOW Level
X = Irrelevant
↑ = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both
registers.
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