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74LV245N View Datasheet(PDF) - NXP Semiconductors.

Part Name74LV245N NXP
NXP Semiconductors. NXP
DescriptionOctal bus transceiver; 3-state
74LV245N Datasheet PDF : 15 Pages
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NXP Semiconductors
74LV245
Octal bus transceiver; 3-state
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VI
G
VCC
VO
DUT
RT
VM
tr
tf
VM
VEXT
RL
CL
RL
001aae331
Fig 7.
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Load circuit for measuring switching times
Table 9. Test data
Supply voltage Input
VCC
< 2.7 V
2.7 V to 3.6 V
VI
VCC
2.7 V
4.5 V
VCC
tr, tf
2.5 ns
2.5 ns
2.5 ns
Load
CL
50 pF
15 pF, 50 pF
50 pF
RL
1 k
1 k
1 k
VEXT
tPHL, tPLH
open
open
open
tPZH, tPHZ
GND
GND
GND
tPZL, tPLZ
2VCC
2VCC
2VCC
74LV245_3
Product data sheet
Rev. 03 — 15 April 2009
© NXP B.V. 2009. All rights reserved.
8 of 15
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General description
The 74LV245 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC245 and 74HCT245.
The 74LV245 is an octal transceiver with non-inverting 3-state bus compatible outputs in both send and receive directions. A send/receive (DIR) input controls direction, and an output enable (OE) input makes easy cascading possible. Pin OE controls the outputs so that the buses are effectively isolated.

Features
■ Wide operating voltage: 1.0 V to 5.5 V
■ Optimized for low voltage applications: 1.0 V to 3.6 V
■ Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
■ Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
■ Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
   Tamb = 25 °C
■ ESD protection:
   ◆ HBM JESD22-A114E exceeds 2000 V
   ◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

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