BC337 View Datasheet(PDF) - NXP Semiconductors.
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| BC337 Datasheet PDF : 0 Pages | |||
µPD17010
13. RESET ........................................................................................................................................... 160
13.1 Configuration of Reset Block ............................................................................................................. 160
13.2 Reset Function .................................................................................................................................... 161
13.3 CE Reset .............................................................................................................................................. 162
13.4 Power-ON Reset .................................................................................................................................. 167
13.5 Relation between CE Reset and Power-ON Reset ........................................................................... 170
13.6 Power Failure Detection ..................................................................................................................... 174
14. PLL FREQUENCY SYNTHESIZER ............................................................................................... 182
14.1 Configuration of PLL Frequency Synthesizer .................................................................................. 182
14.2 Functional Outline of PLL Frequency Synthesizer .......................................................................... 183
14.3 Input Selector Block and Programmable Divider ............................................................................ 184
14.4 Reference Frequency Generator ....................................................................................................... 189
14.5 Phase Comparator (φ-DET), Charge Pump, and Unlock Detection Block ..................................... 191
14.6 PLL Disabled Status ........................................................................................................................... 195
14.7 Using PLL Frequency Synthesizer .................................................................................................... 196
14.8 Status on Reset ................................................................................................................................... 199
15. GENERAL-PURPOSE PORTS ...................................................................................................... 200
15.1 Configuration and Classification of General-Purpose Ports .......................................................... 200
15.2 Functional Outline of General-Purpose Ports .................................................................................. 202
15.3 General-Purpose I/O Ports (P0A, P0B, P0C, and P1A) ................................................................... 207
15.4 General-Purpose Input Ports (P0D and P1D) ................................................................................... 215
15.5 General-Purpose Output Ports (P1B, P1C, and P2A) ...................................................................... 217
15.6 General-Purpose Output Ports (P0E, P0F, P0X, and P0Y) ............................................................... 219
16. A/D CONVERTER (ADC) ............................................................................................................... 227
16.1 Configuration of A/D Converter ......................................................................................................... 227
16.2 Functional Outline of A/D Converter ................................................................................................. 227
16.3 Input Select Block ............................................................................................................................... 228
16.4 Compare Voltage Generator Block .................................................................................................... 230
16.5 Compare Block .................................................................................................................................... 233
16.6 Performance of A/D Converter ........................................................................................................... 234
16.7 Using A/D Converter ........................................................................................................................... 235
16.8 Notes on Using A/D Converter ........................................................................................................... 240
16.9 Reset Status ........................................................................................................................................ 240
17. D/A CONVERTER (DAC) ............................................................................................................... 241
17.1 Configuration of D/A Converter ......................................................................................................... 241
17.2 Functional Outline of D/A Converter ................................................................................................. 241
17.3 Output Select Block ............................................................................................................................ 242
17.4 Duty Setting Block and Clock Generation Block ............................................................................. 244
17.5 Reset Status ........................................................................................................................................ 247
18. CLOCK GENERATOR PORT (CGP) ............................................................................................. 248
18.1 Configuration of Clock Generator Port ............................................................................................. 248
18.2 Functional Outline of Clock Generator Port ..................................................................................... 248
18.3 Output Select Block ............................................................................................................................ 249
18.4 VDP/SG Setting Block and Clock Generation Block ....................................................................... 251
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